MIPS architecture

Microprocessor without interlocked pipeline stages (MIPS) is a microprocessor architecture developed by MIPS Computer Systems Inc

The MIPS CPU family was one of the most successful and flexible CPU designs throughout the 1990s, and has found broad application in embedded systems, Windows CE devices, SGI workstations, and Cisco Internet routers. The Nintendo 64 video game console uses a 64-bit MIPS processor.

The MIPS CPU features a five-stage CPU pipeline to execute multiple instructions at the same time. The CPU has 32 registers, from which two serve special purposes, the rest being available to generic use, regulated through ABI conventions. Popular compilers that target the MIPS architecture include the MIPSPro Compiler and GCC.

Four backward-compatible revisions of the MIPS instruction set exist, named MIPS I to MIPS IV. Several "add-on" extensions are also available, including MIPS-3D which is a simple set of integer-based SIMD instruction set dedicated to common 3D tasks, MIPS16 which adds compression to the instruction stream to make programs take up less room, and the recent addition of MIPS MT, new multithreading additions to the system similar to HyperThreading in the latest Intel lineup.

Because the designers created such a clean instruction set (see Instructions), computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs like HP Precision Architecture and DEC Alpha.

The early MIPS architectures were 32-bit implementations (generally 32 bit wide registers and data paths), later versions were 64-bit implementations.

Table of contents

1 History
2 MIPS CPU family
3 Other models and future plans
4 MIPS cores
5 Further reading
6 MIPS Programing

History

In 1981, a team led by John Hennessy at Stanford University started work on what would become the first MIPS processor. The basic concept was to dramatically increase performance through the use of deep instruction pipelines, a technique that was well known, but difficult to implement. One major barrier to pipelining was that it required locks to be set up to ensure that instructions that took multiple clock cycles to complete would stop the pipeline from loading more data. These locks can take a long time to set up, sometimes as long as short instructions take to complete, so a major design aspect of the MIPS design was to demand that all instructions take only one cycle to complete, thereby removing any needs for locking.

Although this design eliminated a number of useful instructions, notably things like multiply and divide which take multiple steps, it was felt that the overall performance of the system would be dramatically improved by running the chips at much higher clock rates. This ramping of the speed would be difficult with locking involved, as the time needed to set up locks is as much a function of die size as clock rate. The elimination of these instruction became a contentious point, which many observers used to claim the design (and RISC in general) would never live up to its hype.

In 1984 Hennessy was conviced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the R2000, in 1985, improving the design as the R3000 in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in SGI's series of workstations.

In 1991 MIPS released the first 64-bit CPU design, the R4000. The design was so important to SGI, at the time one of their only major customers, that SGI bought the company outright in 1992 in order to guarentee the design would not be lost given the financial difficulties MIPS had while building the design. Becoming an internal group at SGI, the company was now known as MIPS Technologies.

In the early 1990s MIPS started licensing their designs to 3rd arty vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable CISC designs of similar gate count, and therefore price. Sun Microsystems attempted to follow their success by licensing their SPARC core, but have never been anywhere near as successful. By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48th million MIPS-based CPU shipped, making it the first RISC CPU to outship the famous Motorola 68000 family. They were so successful that SGI spun-off MIPS Technologies in 1998.

In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit MIPS32 and 64-bit MIPS64. NEC, Toshiba and SiByte (later acquired by Broadcom) each obtained licenses for the MIPS64 as soon as it was announced. Success followed success, and today the MIPS cores are one of the most-used "heavyweight" cores in the marketplace for computer-like devices (hand-held computers, set-top boxes, etc.), with other designers fighting it out for other niches. Some indication of their success is the fact that Motorola uses MIPS cores in their set-top box designs, instead of their own PowerPC-based cores.

Fully half of MIPS income comes from licensing their designs today, while much of the rest comes from contract design work on cores that will then be produced by 3rd parties.

MIPS CPU family

The first commercial MIPS CPU, model, the R2000, was announced in 1985. It added multiply and divide by including a separate unit for these tasks. In order to do this, the system inserted special "delay slots" into the instruction stream, filling them with other instructions that would complete in one cycle. The instructions were then re-ordered on the way out, placing the results from the math unit back into the main stream of instructions.

The R2000 could be booted either big-endian or little-endian. It had 32 32-bit general purpose registers, but no condition code register, considering it a potential bottleneck, a feature it shares with the AMD 29000. The program counter can be read like other registers.

The R2000 also had support for up to 4 co-processors, one of which was built into the main CPU and handled exceptions and traps, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.

The R3000 succeeded the R2000 in 1988, adding 32kB caches for instructions and data, 64kB total, along with cache coherency support for multi-processor use. However, it turned out that the multiprocessor support was flawed, and the R3000 was not widely used in this way. The R3000 also included a built-in MMU, a common feature on CPUs of the era. The R3000 was the first successful MIPS design in the marketplace, and eventually over 1 million were made. The R3000A was a speed bumped version running at 40MHz that delivered 32 VUPSs (basically equivalent to MIPS). Like the R2000 the R3000 was paired with the R3010 FPU.

The R4000 series, released in 1991, changed the MIPS line to a full 64-bit implementation, and moved the FPU onto the main die to create a single-chip system. However, this left little room on the die, so the caches were reduced to 8kB each. With the introduction of the R4000 a number of improved versions soon followed, including the R4400 of 1993 which included 16kB caches and a controller for another 1MB external (level 2) cache, and the R4600, a speed-bumped R4400, later that same year. A modified version of the R4000 core was used in the Nintendo 64.

The R5000 increased caches to 32kB each, and had certain optimizations over the earlier R4000s that allowed faster graphics processing; mostly, this amounted to the FPU being optimized for single precision. R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement.

The R8000 (1994) was the first superscalar MIPS design, including two R4000-like ALU cores on a single die. This left no room for the FPU, which had to be moved back out to an external chip, and in this now-larger space they included considerably improved performance. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.

The R10000 was the next, and likely last, major step in the MIPS design. Released in 1995 it essentially combined the R8000's two-ALU integer unit with two simplified FPUs on a single die, adding a new out-of-order execution scheduler. Even with the simpler FPU the real performance was better due to faster clock speeds and more cores, and the R10000 quickly replaced all of their earlier designs in SGI hardware.

More recent designs have all been built on the R10000 core. The R12000 used an improved process to shrink the chip and run it at higher clock rates. The R14000 bumped the speed again to up to 600MHz, added support for DDR SRAM in the cache, and increased the computer bus speed to 200MHz for better throughput. The most recent version, the R16000, doubles the size of the caches to 64kB for both the address and data cache, adds support for up to 8MB of level 2 cache, and bumps the clock rates once again, to 700MHz.

Other models and future plans

Other members of the MIPS family include the R6000, a bipolar implementation of the R5000. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared. The R7000 was a version of the R5000 with a built-in 256kB level 2 cache and a controller for optional level three cache. It was primarily targeted at embedded designs, including SGI's graphics processors and various networking solutions, primarily by Cisco. The R9000 name was never used.

At one time SGI had intended to move off the MIPS platform to the Intel Itanium, and development was to have ended with the R10000. The ever-longer delays in introducing the Itanium meant that the installed base of MIPS-based machines continued to increase. By 1999 it was clear that development had ended too soon, and the R14000 and R16000 were created as a result. SGI has hinted at a more complex R8000 style FPU for later R-series, and a dual core processor is probable. Low power consumption / heat dissipation will continue be a focus.

MIPS cores

In recent years most of technology used in the various MIPS generations has been offered as building-blocks for embedded processor designs. Both 32-bit and 64-bit basic cores are offered, known as the 4K and 5K respectively, and the design itself can be licenced as MIPS32 and MIPS64. These cores can be mixed with various add-in units such as FPUs, various input/output devices, etc.

MIPS cores have been very successful, they form the basis of many newer Cisco routers, cable modems and ADSL modems,laser printer engines, set-top boxes, handheld computers, and the Sony PlayStation 2.

These units are widely used in everything from routers to smartcards.

MIPS Programing

There is a freely available "MIPS R2000/R3000 Simulator" called SPIM for several operating systems (i.e., UNIX or GNU/Linux; MS Windows 95, 98, NT, 2000, XP; and DOS) which is good for learning MIPS assembly language programing and the general concepts of RISC-assembly language programing: http://www.cs.wisc.edu/~larus/spim.html

A summary of the R3000 instruction set can be found here.